1. Field of the Invention
The invention relates to a trench capacitor, and more particularly to a method for forming a trench capacitor with a collar dielectric layer to reduce the top width of the trench capacitor.
2. Description of the Related Art
A conventional DRAM cell consists of a MOS and a capacitor, and the capacitor is normally a deep trench capacitor to reduce the size of the memory cell.
FIG. 1A is a top view of a deep trench array of a conventional DRAM. In a folded bit line structure, each active area includes two word lines WL1 and WL2 and a bit line BL. In FIG. 1A, DT is a deep trench and BC is a bit line contact.
FIG. 1B is a cross-section of a deep trench array of a conventional DRAM. A deep trench DT is formed in a semiconductor substrate 10, and a deep trench capacitor 12 having a node dielectric and a storage node is formed in a bottom of the deep trench DT. A method for forming the deep trench capacitor 12 is described as follows. The p+ semiconductor substrate 10 is anisotropically etched to form a deep trench DT. A heavily doped oxide layer, such as ASG, is formed on the sidewall and the bottom of the deep trench DT, and annealed to diffuse ions into the semiconductor substrate 10 of the bottom of the deep trench to form an n+ type diffusion region 14 as a buried plate. A silicon nitride layer 16 is formed on the sidewall and bottom of the deep trench DT as a capacitor dielectric layer. The deep trench DT is filled with a first poly layer 18 doped with n+ type ions, and the poly layer 108 is recessed to a predetermined depth as a storage node of the deep trench capacitor 12.
A collar dielectric layer 20 is formed on a sidewall of a top portion of the deep trench DT, and a second poly layer 22 and a third poly layer 24 are sequentially formed in the deep trench. Word lines WL1 and WL2, S/D 28, a bit line contact BC, and a bit line BL are sequentially formed. DRAMs are separated by STI structures 26.
A buried strap outdiffusion region 30 acting as a node junction is formed in the semiconductor substrate 10 near an opening of the deep trench DT to connect the deep trench capacitor 12 and the MOS on the surface of the semiconductor substrate 10. A method for forming the buried strap outdiffusion region 30 is described as follows. N+ type ions in the second poly layer 22 are diffused into the semiconductor substrate 10 through the third poly layer 24, acting here as a buried strap. The collar dielectric layer 20 isolates the buried strap outdiffusion region 30 and the buried plate 14 effectively to avoid retention time decrease by leakage current from the DRAM.
FIG. 2A to 2E are cross-sections of a conventional method for forming a collar dielectric layer.
In FIG. 2A, the deep trench capacitor 12 in the p+ type semiconductor substrate 10 comprises a pad silicon nitride layer 32, the deep trench DT, the n+ type diffusion region 14, the silicon nitride layer 16, and the first poly layer 18 doped by n+ type ions.
In FIG. 2B, the silicon nitride layer 16 on the top portion of the deep trench DT is removed, and the first poly layer 18 is recessed. The exposed semiconductor substrate 10 is oxidized to form a first oxide layer 34 covering a sidewall of the top portion of the deep trench. The first oxide layer 34 isolates the n+ type diffusion region 14 and the buried strap outdiffusion region 30.
In FIG. 2C, a second oxide layer 36 is deposited by CVD, and anisotropic etching is performed to remove portions thereof from the first poly layer 18.
In FIG. 2D, the second poly layer 22 doped by n+ type ions is deposited in the deep trench DT, and the second poly layer 22 is recessed to a predetermined depth.
In FIG. 2E, a portion of the first oxide layer 34 and second oxide layer 36 are removed by wet etching until the top portion of the second poly layer 22 protrudes. The collar dielectric layer 20 consists of the remaining first oxide layer 34 and the remaining second oxide layer 36.
When forming the first oxide layer 34, a portion of the semiconductor substrate 10 is transformed into SiO2, and removed by wet etching. Thus, the size of the top portion of the deep trench 34 is increased.
Overlap tolerance between the word line WL and the deep trench DT is decreased, and the overlap region L between S/D diffusion region 28 and the buried strap outdiffusion region 30 is reduced. Serious current leakage occurs in the buried strap outdiffusion region 30, affecting a sub-Vt. The process of forming the first oxide layer 34 increases the top width of the deep trench DT. If the process is omitted, leakage current between the n+ type diffusion region 14 and the buried strap outdiffusion region 30 is substantially increased.